1. Field of the Invention
The present invention relates to a memory device and method for manufacturing the same. More particularly, the present invention relates to a single electron memory device having quantum dots between a gate electrode and a single electron storage element and method for manufacturing the same.
2. Description of the Related Art
As the size of a metal-oxide-semiconductor field effect transistor (MOSFET) becomes smaller, problems arise that do not occur in larger devices. Thus, it becomes difficult to further reduce the size of the MOSFET. For example, as the size of the MOSFET device becomes smaller, problems occur such as lowering of threshold voltage caused by a decrease in effective channel length, drain induced barrier lowering (DIBL), punch-through, deterioration of a gate oxide layer, and an increase in leakage current due to hot carriers generated by an increase in the electrical field in the device. These problems complicate further reduction in the size of a MOSFET.
The most significant problem to be solved by continuously scaling the MOSFET to the range of nanometers (nm) is a physical limit. At the physical limit, the number of electrons participating in the operation of the device becomes similar to the number of thermally fluctuating electrons. Thus, proper operation of a miniaturized MOSFET at room temperature is not expected.
To overcome this problem, development of a new device structure, which may replace the current complementary MOSFET (CMOSFET) structure, is required. Recently, a single electron transistor (SET) has been studied as an alternative new device.
Coulomb blockade is a physical principle of the single electron device. In the single electron device, Coulomb blockade is a condition wherein tunneling is blocked under specific conditions. The specific conditions for Coulomb blockade are when the free energy of a total system, consisting of a charging energy and an electrostatic energy for a junction capacitance, increases or decreases when electrons tunnel through a minute size tunnel junction.
The SET is a switching device that controls current flowing through two tunnel junctions between quantum dots by controlling the Coulomb blockade conditions. The Coulomb blockade occurs through a gate potential, which is capacitively coupled to the quantum dots.
Quantum dots, which are coupled to a channel through a tunnel junction, are used as a storage electrode in a single electron memory device. The single electron memory device is a memory device for recognizing a variation in channel current due to charges stored in the quantum dots as information, xe2x80x9c0xe2x80x9d or xe2x80x9c1.xe2x80x9d
Unlike in the MOSFET, the effects caused by thermal fluctuation decrease in the single electron device as the device becomes smaller. A property of the device is determined by the capacitance between the elements constituting the device rather than by the structure of the device. Thus, the single electron device is advantageous for device scaling.
Conventional single electron memory devices store electrons in a single quantum dot 14, as shown in FIG. 1 or in a hybrid structure having a high distribution density nano-crystal array 20, as shown in FIG. 2. In both structures, a MOSFET is used as a sense device. In FIGS. 1 and 2, reference numeral 10 denotes a substrate, reference characters S and D denote a source and a drain, and reference characters G and G1 denote a gate lamination.
In FIG. 1, the gate lamination G includes a tunneling oxide layer 12 formed on the substrate 10 between a source S and a drain D, a single quantum dot 14, and a control oxide layer 16 and a gate electrode 18, which cover the single quantum dot 14. In FIG. 2, the gate lamination G1 is similar to the gate lamination G of FIG. 1 but includes a nano-crystal array 20, instead of the single quantum dot 14.
The quantum dot 14 of the single electron memory device shown in FIG. 1 is formed using a nano-lithography technique. The nano-crystal array of the single electron memory device shown in FIG. 2 is formed utilizing a self-assembled growth method.
In the single electron memory devices, the thickness of the tunneling oxide layer 12 is the main factor determining the reliability of the device, retention time of information and speed of write/erase. The thickness of the control oxide layer 16 and the distribution density of the quantum dot are the main factors determining the extent of variation in threshold voltage.
In the conventional single electron memory devices, however, the quantum dot or the nano-crystal array is formed directly on the tunneling oxide layer 12, and thus, defects may occur in the tunneling oxide layer 12 while forming the quantum dot or the nano-crystal array. These defects may result in changes in the properties of the device thereby requiring many limitations in the formation of the quantum dot on the tunneling oxide layer 12.
For example, in order to implement single electron tunneling at room temperature when the quantum dot is formed of silicon, preferably, the size of the quantum dot is less than 10 nm. It is difficult, however, to form the quantum dot having a predetermined size due to the possibility of causing defects in the tunneling oxide layer. Hence, it becomes difficult to manufacture a single electron memory device, which operates at room temperature. Further, in the prior art single electron memory device, the retention time of information does not reach a practical standard.
A feature of an embodiment of the present invention provides a single electron memory device having quantum dots or an element having the same effect, which retains information long enough to be practical and prevents variation in the properties of the device.
Another feature of an embodiment of the present invention provides a method for manufacturing a single electron memory device.
An embodiment of the present invention provides a single electron memory device, including a substrate on which a nano-scale channel region is formed between a source and a drain, and a gate lamination pattern including quantum dots on the channel region.
The gate lamination pattern includes a lower layer formed on the channel region, a single electron storage medium formed on the lower layer for storing a single electron tunneling through the lower layer, an upper layer including quantum dots formed on the single electron storage medium, and a gate electrode formed on the upper layer to be in contact with the quantum dots.
The quantum dots are included in the upper layer and are isolated from the single electron storage medium. It is another feature of an embodiment of the present invention that the quantum dots contact the single electron storage medium and the gate electrode.
The upper layer is formed of a first and a second upper layer, and the quantum dots are formed in the second upper layer.
The single electron storage medium in an embodiment of the present invention is formed of a material selected from the group consisting of silicon nitride (Si3N4) or PZT having quantized trap sites at an interface with the lower layer or in the bulk, silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), and a metal.
According to another feature of the present invention, there is provided a single electron memory device. The device includes a substrate on which a nano-scale channel region is formed between a source and a drain and a gate lamination pattern including quantum dots on the channel region. The gate lamination pattern includes a lower layer, an upper layer, and a gate electrode, which are sequentially formed on the channel region, and vertically spaced-apart first and second quantum dots included in the upper layer. The first quantum dots are in contact with the lower layer and the second quantum dots are in contact with the bottom surface of the gate electrode.
According to yet another feature of the present invention, there is provided a single electron memory device. The device includes a substrate on which a nano-scale channel region is formed between a source and a drain and a gate lamination pattern including quantum dots on the channel region. The gate lamination pattern includes a lower layer formed on the channel region, a single electron storage means formed on the lower layer for storing a single electron tunneling through the lower layer, an upper layer covering the single electron storage means, an upper surface of the upper layer being uneven, and a gate electrode formed on the upper layer.
The single electron storage means is formed of a material selected from the group consisting of silicon nitride (Si3N4), PZT, silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), and a metal. The single electron storage means may also be quantum dots formed on the lower layer. The quantum dots are formed of a material selected from the group consisting of silicon nitride, silicon, silicon germanium, gallium arsenide, and a metal.
A further feature of the present invention provides a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET. Forming the gate lamination pattern includes (a) sequentially forming a lower layer and a single electron storage medium for storing a single electron tunneling through the lower layer on a substrate, (b) forming an upper layer including quantum dots on the single electron storage medium, (c) forming a gate electrode layer on the upper layer to be in contact with the quantum dots, and (d) patterning the lower layer, the single electron storage medium, the upper layer, and the gate electrode layer, in reverse order.
Forming the upper layer may include forming a first upper layer on the single electron storage medium, forming the quantum dots on the first upper layer, and forming a second upper layer to cover the quantum dots on the first upper layer. Forming a gate electrode layer may further include polishing the upper layer until the quantum dots are exposed.
In another feature of the present invention there is provided a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET, wherein forming the gate lamination pattern includes (a) forming a lower layer on a substrate, (b) forming an upper layer including vertically spaced-apart first and second quantum dots on the lower layer, (c) forming a gate electrode on the upper layer to be in contact with the second quantum dots, and (d) patterning the lower layer, the upper layer, and the gate electrode, in reverse order. Forming the upper layer may include forming the first quantum dots on the lower layer to store a single electron tunneling through the lower layer, forming a first upper layer to a thickness sufficient to cover the first quantum dots, forming the second quantum dots on the first upper layer, and forming a second upper layer to cover the second quantum dots on the first upper layer.
In still another feature of the present invention, there is provided a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET. Forming the gate lamination pattern includes (a) forming a lower layer on a substrate, (b) sequentially forming a single electron storage means for storing a single electron tunneling through the lower layer and an upper layer covering the single electron storage means on the lower layer, wherein the surface of the upper layer is uneven, (c) forming a gate electrode layer on the upper layer, and (d) patterning the lower layer, the single electron storage means, the upper layer, and the gate electrode layer, in reverse order. The single electron storage means is quantum dots or the single electron storage medium.
Preferably, the lower layer may be formed of a material selected from the group consisting of silicon oxide (SiO2), alumina (Al2O3), tantalum oxide (TaO2), titanium oxide (TiO2), HfO2 and ZrO2. Preferably, the upper layer may be formed of a material selected from the group consisting of silicon oxide (SiO2), alumina (Al2O3), tantalum oxide (TaO2), and titanium oxide (TiO2). Preferably, the gate electrode may be formed of a material selected from the group consisting of doped Si, doped SiGe, doped GaAs, a metal, a silicide, and a polycide. Preferably, the quantum dots are formed of Si.
The single electron memory device according to an embodiment of the present invention includes a silicon nitride layer as a nano-scale storage medium between quantum dots, which are included on the bottom surface of a gate electrode, and a tunneling layer formed on a nano-scale channel region. As a result, the silicon nitride layer may be locally charged even in a nano-scale, and may retain information longer than a conventional single electron memory device using quantum dots as a data storage electrode. Further, in the present invention, the quantum dots are not included on a lower layer as a tunneling layer, but in an upper layer, thereby maintaining the properties of a device and allowing the quantum dots to be formed by various methods.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.